职位诱惑
Job Description:
- Responsible for die size estimation, floor-planning, power planning and power analysis.
- Responsible for low power SOC physical design.
- Responsible for block level CPF design, Logic/physical synthesis, Clock tree synthesis, place and routing, STA, SI, timing closure.
- Responsible for DFM, DRC/LVS physical verification.
Qualifications:
- 4th year college student or 2nd year of post graduate student.
- Major in computer science, electronic engineering or equivalent.
- Good language skill in English.
- Basic experience in IC physical implementation is a plus.
- Experience using backend EDA tools; i.e. Cadence Virtuoso, RC, EDI, ETS, EPS, Mentor Graphics Calibre etc is a plus.
- Relevant experience in the area of digital circuit design is a plus.
- Good knowledge of C/C++, Perl/TCL, scripts in Linux/Unix environment is a plus.X
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