Responsibilities:

-        Responsible for whole chip or sub system level DFT architecture definition and DFT planning for complex SoC design;

-         Perform design implementation and verification on test modules, scan insertion, test compression, Memory Build In Self Test, JTAG/Boundary scan.

-        Be responsible to improve the testability of IP and chip to meet test coverage requirement.

-        Be responsible for scan pattern generation, BIST and boundary scan pattern generation and verification.

-        Serve as the focal point for the SoC team in interfacing with Test Engineer and Product Engineer to define the DFT requirement, deliver test patterns and provide support on silicon test debug.

Requirements:

-        4th year college student or 2nd year of post graduate student major in Communications, Microelectronics Engineering and Computer Science.

-        Strong logic design and verification background with good debugging capability, Experience in digital design with good knowledge of SoC design flow, including RTL coding, simulation, synthesis, DFT and silicon test.

-        Familiar with industrial standard DFT methodology and tools, Experience on scan, ATPG, memory BIST, LBIST, T, Boundary scan, etc.

-         Analog/flash design knowledge/background will be a strong plus.

-        Knowledge in ATE  and experience in silicon validation on tester will be plus.

-        script language like perl, tcl.will be nice to have skill.